This invention relates to video graphics systems and particularly to systems for generating complex graphic images on raster display screens.
Computer-generated images of landscapes and the like formed from terrain maps stored in computer memory are finding increasing use in flight simulation and real-time animation systems. High speed graphics systems are also finding use in computer-aided design (CAD) systems for computer simulation of dynamic behavior of automobiles, aircraft, engines and machine parts. True high-speed color graphics systems have heretofore required complex and very expensive hardware.
Generating complex images on a CRT at real-time rates of 24 or more frames per second requires the ability to rapidly draw graphical primitives, i.e., points, lines and polygons, into a display memory, or frame buffer. Vector generators, which can render a line drawing of an object, given its end points, by moving a cathode ray tube (CRT) beam continuously from a starting point to an ending point, have been employed to draw polygonal areas. However, with this technique, a multi-sided filled-in polygon which is to be drawn must be decomposed into a group of straight lines and a separate command must be given for each line which is to drawn. This technique seriously hinders the system's ability to draw complex imges in real time.
Raster displays, which use horizontal scan lines like a conventional television, fill inside areas of polygons easily, however again, the overall speed with which geometric shapes can be drawn is too slow for real-time simulation. An entire frame of pixel data is stored in the frame buffer in the raster display system. Conventionally, the picture information for each pixel has been calculated individually by a host processor and stored sequentially into the frame buffer. This information is then read from the frame buffer in synchronism with the active scan of the display beam to display the polygonal area. An exorbitant amount of host processor time is required for the calculations necessary to fill the frame buffer, such that real-time simulations and animation are not possible with standard microprocessors. CRT controller chips can draw about 10 times as fast as microprocessors but still fall far short of the speed required for real-time graphics display.
A technique for increasing the speed with which three dimensional images can be handled in graphics systems involves two processors, a host processor and a video processor, operated in parallel and communicating with each other by instructions left in a common memory area. The host processor handles all the mathematical manipulations of the X, Y and Z coordinates of each vertex for each polygon in a three dimensional scene and outputs corresponding X and Y coordinates for a two dimensional projection from a given vantage point into the common memory area.
Sherman, in U.S. Pat. No. 4,425,559, shows a raster-type polygon display apparatus which generates polygonal areas displayed by creating line segments that are used to form boundaries of the polygonal areas. A microprocessor supplies binary information describing each line segment boundary in terms of the X and Y coordinates of the line's starting point, the slope of the line segment, and the horizontal scan line in which the line segment terminates. During generation of each horizontal line, the binary information for each line segment is accessed from a shared RAM and checked to determine if the line segment is to appear on the display screen during the next successive horizontal scan line. If so, the color data word is used as a control signal and is stored in a line buffer RAM at a memory location corresponding to the horizontal position of the line segment on the next successive horizontal line. During the display scan of the next succeeding horizontal line, the memory locations of the output line buffer are read in synchronism with the movement display beam. As each control signal is encountered and accessed, it is used to set the chroma and luminance of the beam until changed by the next encountered control signal. Two line buffers are employed, and as one line buffer is being read, data for the next succeeding horizontal line is being written into the other line buffer.
The Sherman technique requires the host processor to calculate the slope of all line segments, a time-consuming task because the calculation involves a division process. The speed of this system is necessarily limited as a result. Furthermore, this apparatus returns the scanning beam to the background color/luminance state once the right line segment boundary of a polygon is reached. The display of general background color and luminance on the display screen results in a severe limitation of the system in that overlapping polygons may not be displayed without rendering the right side of a partially covered polygon invisible.